Reading the contents of memory cells generally involves sensing the current or voltage of the cell. Many kinds of sensing schemes are known in the art for memory cell arrays, such as flash or other non-volatile memories. One type of sensing scheme involves comparing the sensed cell to a reference cell.
Reference is now made to FIG. 1, which illustrates a prior art example of an AC matching scheme between an array sensed cell and a reference cell.
As is well known in the art, a typical memory cell (e.g., virtual ground) array 10, such as non-volatile memory (NVM) cell array, may include a plurality of memory cells 12 connected to word lines and to local bit lines 16. The local bit lines 16 may be connected to global bit lines (GBLs) 18 via select transistors 20. The array 10 may be divided into one or more sectors 22, such as by means of isolation zones. The isolated slices 22 may be segmented in the bit line direction by the select transistors 20, and the select transistors 20 may be arranged in distinct areas in the array 10. This segmentation creates isolated physical sectors. More than one physical sector may share common global bit lines 18. Memory cells 12 in physical sectors that share the same global bit lines 18 may not interact due to the isolating select transistors 20.
A bit line (BL) driver 24 drives the drain side of the sensed cell 12. The BL driver 24 is connected to the sensed cell 12 via a YMUX (Y multiplexer) 26, via a driving path that includes one of the GBLs 18, one of the select transistors 20 and one of the local bit lines 16, which, in this case, serves as a drain diffusion bit-line (DBL). The connecting line to which the select transistor 20 is connected is referred to as select line 14 (designated as select line SEL [8:0] in FIG. 1), and the connecting line in the YMUX 26 is referred to as the BS line.
A sense amplifier 28 senses the source side of the sensed cell 12. The path from the source of the sensed cell 12 to the sense amplifier 28 is through one of the local bit lines 16, which, in this case, serves as a source diffusion bit-line, one of the select transistors 20, one of the GBLs 18 and the YMUx 26.
A reference cell 30 is used for the sense amplifier 28. The reference cell 30 is located in a reference mini-array 32. To match the path of the reference cell 30 to that of the sensed cell 12, a matched reference BL (REF-BL) driver 34 is used in conjunction with a reference YMUX (REF-YMUX) 36, reference select transistors 38 (also referred to as ref-select transistors) and matched reference DBLs (REF-DBL) 40. Since most of the capacitance of the array cell path is the GBL capacitance (due to both to GND and coupling capacitance), reference GBLs (REF-GBLs) 42 are used to load the source side and the drain side of the reference path. The connecting line to which the ref-select transistor 38 is connected is referred to as the REF_SEL line, and the connecting line in the YMUX. 36 is referred to as the REF_BS line.
Such a reference scheme is described in U.S. Pat. No. 6,535,434, to Maayan, Sofer, Eliyahu and Eitan, assigned to the same assignee of the present application, the disclosure of which is incorporated herein by reference. In brief, U.S. Pat. No. 6,535,434 describes an architecture and method for implementing a non-strobed operation on an array cell, in which a reference unit is provided for emulating the response of the array cell during a desired operation (e.g., read, program verify, erase verify or other types of read operations). The architecture and method permit relatively noise-free array cell interrogations at close to ground voltage levels.
The read operation is performed by means of selecting the appropriate BS and SEL lines connecting the drain side of the array cell 12 to the BL driver 24 (at node BL_D) and by means of enabling the appropriate BS and SEL lines connecting the source side of the array cell 12 to the sense amplifier 28 (at node BL_S). In addition the same procedure is applied for the reference cell 30, i.e. enabling the appropriate REF_SEL and REF_BS lines to supply drain voltage from the REF_BL driver 34 (at node REF_BL_D) and connecting the source side of the reference cell 30 to the sense amplifier 28 (at node BL_REF). Once all nodes stabilize, the sensing period starts by floating the sense amplifier (SA) inputs. This leads to charging of the SA inputs by the array cell 12 and the reference cell 30, respectively.
Reference is now made to FIG. 2, which illustrates the signals generated at the inputs of the SA 28 with a 1C:1C load capacitance ratio matching scheme. “1C:1C load capacitance ratio matching” means that the capacitance for the sensed cell path and the capacitance for the reference signal path are fully matched. Time T1 represents the time of stabilization of the different nodes. Between the times T1 and T2, the signals BL_S and BL_REF are generated respectively by the array cell 12 and the reference cell 30 charging the total path capacitance. The difference between the signals BL_S and BL_REF depends only on the different programming level of the cells 12 and 30. The reference cell 30 is programmed so that its current level would be between a programmed array cell and an erased array cell. Between times T2 and T3, a decision circuit is used for providing logical output describing the analog output of the SA 28.
In the above-described sensing scheme, the matching between the reference path and the sensed cell path is maintained by copying the sensed cell path to the reference path. This has the disadvantage of multiplying the power dissipation during the sensing period and has a large area penalty. Specifically, in the illustrated example of FIG. 1, the area penalty is two GBLs 18 per sense amplifier 28 and the power penalty is due to the need to drive two drain side GBLs for each read sequence.